The Field Effect Transistor
The transistor is a solid state semiconductor device which can be used for amplification, switching, voltage stabilization, signal modulation and many other functions. Generally, a transistor has three terminals, and a voltage applied to a specific one of the terminals controls current flowing between the other two terminals. One type of transistor is known as the field effect transistor (FET).
The terminals of a field effect transistor (FET) are commonly named source (S), gate (G) and drain (D). In the FET, a small amount of voltage is applied to the gate (G) in order to control current flowing between the source (S) and the drain (D). In FETs the main current appears in a narrow conducting channel formed near (usually primarily under) the gate. This channel connects electrons from the source terminal to the drain terminal. The channel conductivity can be altered by varying the voltage applied to the gate terminal, enlarging or constricting the channel and thereby controlling the current flowing between the source and the drain.
FIG. 1 illustrates a FET 100 comprising a p-type substrate (or a p-well in the substrate), and two spaced-apart n-type diffusion areas—one of which will serve as the “source”, the other of which will serve as the “drain” of the transistor. The space between the two diffusion areas is the “channel”. A thin dielectric layer is disposed over the substrate in the neighborhood of the channel, and a “gate” structure is disposed over the dielectric layer atop the channel. (The dielectric under the gate is also commonly referred to as “gate oxide” or “gate dielectric”.) Electrical connections (not shown) may be made to the source, the drain, and the gate. The substrate may be grounded, or it may be biased at a desired voltage depending on applications.
Generally, when there is no voltage on the gate, there is no electrical conduction (connection) between the source and the drain. As voltage (of the correct polarity) is applied to the gate, there is a “field effect” in the channel between the source and the drain, and current can flow between the source and the drain, and can be controlled by the voltage applied to the gate. In this manner, a small signal (gate voltage) can control a relatively large signal (current flow between the source and the drain).
FET 100 is exemplary of a MOSFET (metal oxide semiconductor FET) transistor. With the specified “n” and “p” types shown above, an “n-channel MOSFET” can be formed. With opposite polarities (swapping “p” for “n” in the diffusions, and “n” for “p” in the substrate or well), a p-channel FET can be formed. In CMOS (complementary metal oxide semiconductor), both n-channel and p-channel MOS transistors may be used, and are often paired with one another.
An integrated circuit (IC) device may comprise many millions of FETs on a single semiconductor “chip” (or “die”), measuring only a few centimeters on each side. Several IC chips may be formed simultaneously, on a single “wafer”, using conventional semiconductor fabrication processes including deposition, doping, photolithography, and etching. After all the chips are formed, they can be singulated from the wafer.
The Floating Gate Transistor
A floating gate transistor is generally a transistor structure, broadly based on the FET, as described hereinabove. As illustrated in FIG. 2, the floating gate transistor 200 has a source and a drain, but rather than having only one gate, it has two gates which are called control gate (CG) and floating gate (FG). It is this arrangement of control gate and floating gate which enables the floating gate transistor to function as a memory cell, as described hereinbelow.
The floating gate is disposed over tunnel oxide (comparable to the gate oxide of the FET). The floating gate is a conductor, and the tunnel oxide is an insulator (dielectric material). Another layer of oxide (interpoly oxide, also a dielectric material) separates the floating gate from the control gate.
Since the floating gate is a conductor, and is surrounded by dielectric material, it can store a charge. Electrons can move around freely within the conductive material of the floating gate (which comports with the basic definition of a “conductor”).
Since the floating gate can store a charge, it can exert a field effect on the channel region between the source and the drain, in a manner similar to how a normal FET works, as described hereinabove. Mechanisms for storing charges on the floating gate structure, as well as removing charges from the floating gate, are described hereinbelow.
Generally, if a charge is stored on the floating gate, this represents a binary “1”. If no charge is stored on the floating gate, this represents a binary “0”. (These designations are arbitrary, and can be reversed so that the charged state represents binary “0” and the discharged state represents binary “1”.) That represents the programming “half” of how a floating gate memory cell operates. The other half is how to determine whether there is a charge stored on the floating gate—in other words, to “read” the memory cell. Generally, this is done by applying appropriate voltages to the source, drain and gate terminals, and determining how conductive the channel is. Some modes of operation for a floating gate memory cell are described hereinbelow.
Normally, the floating gate non-volatile memory (NVM) cell has only a single “charge-storing area”—namely, the conductive floating gate (FG) structure, and can therefore only store a single bit of information (binary “1” or binary “0”). More recently, using a technology referred to as “multi-level cell” (MLC), two or more bits can be stored in and read from the floating gate cell.
The NROM Memory Cell
Another type of memory cell, called a “nitride, read only memory” (NROM) cell, has a charge-storage structure which is different from that of the floating gate memory cell and which permits charges to be stored (or trapped) in two separate charge-storage areas. Generally, the two separate charge storage areas are located within a non-conductive layer disposed between the gate and the underlying substrate, such as a layer of nitride formed in an oxide-nitride-oxide (ONO) stack underneath the gate. The non-conductive layer acts as a charge-trapping medium. Generally, electrical charges will stay where they are put in the charge-trapping medium, rather than being free to move around as in the example of the conductive floating gate of the floating gate memory cell. A first bit of binary information (binary “1” or binary “0”) can be stored in a first portion (such as the left-hand side) of the charge-trapping medium, and a second bit of binary information (binary “1” or binary “0”) can be stored in a second portion (such as the right-hand side) of the charge-trapping medium. An alternative viewpoint is that different charge concentrations can be considered for each bit of storage. Using MLC technology, at least two bits can be stored in and read from each of the two portions (charge storage areas) of the charge-trapping medium (for a total of 4 bits), similarly 3 bits or more than 4 bits may be identified.
FIG. 3 illustrates a basic NROM memory cell 300, which may be viewed as an FET with an “ONO” structure inserted between the gate and the substrate. (One might say that the ONO structure is “substituted” for the gate oxide of the FET.)
The ONO structure is a stack (or “sandwich”) of bottom (lower) oxide 322, a charge-trapping material such as nitride 324, and a top (upper) oxide 326. The ONO structure may have an overall thickness of approximately 10-25 nm, such as 18 nm, as follows:                the bottom oxide layer 322 may be from 3 to 6 nm, for example 4 nm thick;        the middle nitride layer 324 may be from 3 to 8 nm, for example 4 nm thick; and        the top oxide layer 326 may be from 5 to 15 nm, for example 10 nm thick.        
The NROM memory cell has two spaced apart diffusions 314 and 316 (which can function as source and drain, as discussed hereinbelow), and a channel region 320 defined in the substrate 312 between the two diffusion regions 314 and 316, and a gate 328 disposed above the ONO stack 321.
In FIG. 3, the diffusions are labeled “N+”. This means that they are regions in the substrate that have been doped with an electron donor material, such as phosphorous or arsenic. These diffusions are typically created in a larger region which is a p-type cell well (CW) doped with boron (or indium or both). This is the normal “polarity” for an NVM cell employing electron injection (but which may also employ hole injection, such as for erase). With opposite polarity (boron or indium implants in an n-type cell well), the primary injection mechanism would be for holes, which is generally accepted to be not as effective as electron injection. One skilled in the art will recognize that the concepts disclosed herein can be applied to opposite polarity devices.
The charge-trapping material 324 is non-conductive, and therefore, although electrical charges can be stored in the charge-trapping material, they are not free to move around, they will generally stay where they are stored. Nitride is a suitable charge-trapping material. Charge trapping materials other than nitride may also be suitable for use as the charge-trapping medium. One such material is silicon dioxide with buried polysilicon islands. A layer (324) of silicon dioxide with polysilicon islands would be sandwiched between the two layers of oxide (322) and (326). Alternatively, the charge-trapping layer 324 may be constructed by implanting an impurity, such as arsenic, into a layer of silicon dioxide deposited on top of the bottom oxide 322.
Memory cell 300 is generally capable of storing at least two bits of data—at least one bit(s) in a first storage area of the nitride layer 324 represented by the dashed circle 323, and at least one bit(s) in a second storage area of the nitride layer 324 represented by the dashed circle 325. Thus, the NROM memory cell can be considered to comprise two “half cells”, each half cell capable of storing at least one bit(s). It should be understood that a half cell is not a physically separate structure from another half cell in the same memory cell. The term “half cell”, as it may be used herein, is used herein only to refer to the “left” or “right” bit storage area of the ONO stack 321 (nitride layer 324). Storage areas 325, 323 may variously be referred to as “charge storage areas”, “charge trapping areas”, and the like, throughout this document. (The two charge storage areas may also be referred to as the right and left “bits”.)
Each of storage areas 325, 323 in the charge-trapping material 324 can exert a field effect on the channel region 320 between the source and the drain, in a manner similar to how a normal FET works, as described hereinabove (FIG. 2).
Generally, if a charge is stored in a given storage area of the charge-trapping material, this represents a binary “1”, and if no charge is stored in a given storage area of the charge-trapping material, this represents a binary “0”. (Again, these designations are arbitrary, and can be reversed so that the charged state represents binary “0” and the discharged state represents binary “1”.) That represents the programming “half” of how an NROM memory cell operates. The other half is how to determine whether there is a charge stored in a given storage area of the charge-trapping material—in other words, to “read” the memory cell. Generally, this is done by applying appropriate voltages to the diffusion regions (functioning as source and drain) and gate terminals, and determining how conductive the channel is.
Modes of Operation
Generally, the modes of operation for any NVM memory cell (either floating gate or NROM) include “program”, “erase” and “read”. Modes of operation for NROM are now discussed.
Program generally involves injecting electrons into the charge storage areas of the NROM or other NVM cell, typically by a process known as channel hot electron (CHE) injection. Exemplary voltages to program (by CHE injection of electrons) the right bit (right bit storage area) of an NROM cell may include:                the left BL (acting as source, Vs) is set to 0 volts        the right BL (acting as drain, Vd) is set to +5 volts        the gate (Vg) is set to +8-10 volts        the substrate (Vb) is set to 0 volts and the bit storage area above the drain (right BL) becomes programmed To program the left bit storage area, source and drain are reversed—the left bitline serves as the drain and the right bitline serves as the source.        
Erase may involve injecting holes into the charge storage areas of the NROM cell, typically by a process known as hot hole injection (HHI). Generally, holes cancel out electrons (they are electrically opposite), on a one-to-one basis. Exemplary voltages to erase (by HHI injection of holes) the right bit of an NROM cell may include:                the left BL (acting as source, Vs) is set to float        the right BL (acting as drain, Vd) is set to +5 volts        the gate (Vg) is set to −7 volts        the substrate (Vb) is set to 0 voltsand the bit storage area above the drain (right BL) becomes erased. To erase the left bit storage area, source and drain are reversed—the left bitline serves as the drain, and the right bitline serves as the source.        
Read may involve applying voltages to the terminals of the memory cell and, based on subsequent current flow, ascertaining the threshold voltage of the charge storage area within the cell. Generally, to read the right bit of the NROM cell, using “reverse read”,                the right BL (acting as source, Vs) is set to 0 volts        the left BL (acting as drain, Vd) is set to +2 volts        the gate (Vg) is set to +5 volts        the substrate (Vb) is set to 0 voltsand the bit storage area above the source (right BL) can be read. To read the left bit storage area, source and drain are reversed—the left bitline serves as the source, and the right bitline serves as the drain.“Reading” an NROM Cell        
Reading an NROM memory cell may involve applying voltages to the terminals of the memory cell comparable to those used to read a floating gate memory cell, but reading may be performed in a direction opposite to that of programming Generally, rather than performing “symmetrical” programming and reading (as is the case with the floating gate memory cell, described hereinabove), the NROM memory cell is usually programmed and read “asymmetrically”, meaning that programming and reading occur in opposite directions. This is illustrated by the arrows in FIG. 3. Programming is performed in what is termed the forward direction and reading is performed in what is termed the opposite or reverse direction. For example, generally, to program the right storage area 323 (in other words, to program the right “bit”), electrons flow from left (source) to right (drain). To read the right storage area 323 (in other words, to read the right “bit”), voltages are applied to cause electrons to flow from right to left, in the opposite or reverse direction. For example, generally, to program the left storage area 325 (in other words, to program the left “bit”), electrons flow from right (source) to left (drain). To read the left storage area 325 (in other words, to read the left “bit”), voltages are applied to cause electrons to flow from left to right, in the opposite or reverse direction. See, for example, U.S. Pat. No. 6,768,165.
“Read” is generally done by measuring the Vt of a cell (or half-cell), and associating the measured Vt with a program level (such as “0” or “1”). Although the Vts of the cells are measured on an individual basis, it is generally necessary to determine a distribution of Vts for many cells in order to associate the measured Vt of a given cell with a program level, with confidence. For example—if only one cell were to be read, and its threshold voltage were to be found to be at or very near the RV between two program levels, it may be difficult to say, with certainty, at which of two program levels the single cell was programmed, since its threshold voltage may have moved slightly upward or slightly downward since it was programmed. This is a benefit of reading bits one block at a time—to obtain a statistically meaningful sample of Vt's across a number of cells.
Memory Array Architecture, Generally
Memory arrays are well known, and comprise a plurality (many, including many millions) of memory cells organized (including physically arranged) in rows (usually represented in drawings as going across the page, horizontally, from left-to-right) and columns (usually represented in drawings as going up and down the page, from top-to-bottom).
As discussed hereinabove, each memory cell comprises a first diffusion (functioning as source or drain), a second diffusion (functioning as drain or source) and a gate, each of which has to receive voltage in order for the cell to be operated, as discussed hereinabove. Generally, the first diffusions (usually designated “source”) of a plurality of memory cells are connected to a first bit line, which may be designated “BL(n)”, and second diffusions (usually designated “drain”) of the plurality of memory cells are connected to a second bit line which may be designated “BL(n+1)”. Typically, the gates of a plurality of memory cells are connected to common word lines (WL).
The bitlines may be “buried bitline” diffusions in the substrate, and may serve as the source/drain diffusions for the memory cells. The wordlines may be polysilicon structures and may serve as the gate elements for the memory cells.
FIG. 4 illustrates an array of NROM memory cells (labeled “a” through “i”) connected to a number of word lines (WL) and bit lines (BL). For example, the memory cell “e” has its gate connected to WL(n), its source (left hand diffusion) is connected to BL(n), and its drain (right hand diffusion) is connected to BL(n+1). The nine memory cells illustrated in FIG. 4 are exemplary of many millions of memory cells that may be resident on a single chip.
Notice, for example that the gates of the memory cells “e” and “f” (to the right of “e”) are both connected to the same word line WL(n). (The gate of the memory cell “d” to the left of “e” is also connected to the same word line WL(n).) Notice also that the right hand terminal (diffusion) of memory cell “e” is connected to the same bit line BL(n+1) as the left-hand terminal (diffusion) of the neighboring memory cell “f”. In this example, the memory cells “e” and “f” have two of their three terminals connected together.
The situation of neighboring memory cells sharing the same connection—the gates of neighboring memory cells being connected to the same word line, the source (for example, right hand diffusion) of one cell being connected to the drain (for example left hand diffusion) of the neighboring cell—is even more dramatically evident in what is called “virtual ground architecture” wherein two neighboring cells actually share the same diffusion. In virtual ground array architectures, the drain of one memory cell may actually be the same diffusion which is acting as the source for its neighboring cell. Examples of virtual ground array architecture may be found in U.S. Pat. Nos. 5,650,959; 6,130,452;  and 6,175,519, incorporated in their entirety by reference herein.
The bitlines (BLs) mentioned above may extend in parallel with one another, through the array (or a portion thereof). A single buried bitline (BB) may be a single diffusion shared by two adjacent cell transistors, and may be referred to herein as a diffusion bitline (DBL). The diffusion bitline (DBL) is a diffusion, functioning as a conductive line, which is physically disposed (“buried”) within the surface of the substrate.
A cell transistor may be formed by an ONO stack, which is disposed on the surface of the substrate, generally between adjacent bitlines (BB, dbl). The ONO stack includes a layer of silicon nitride (nitride), which can trap (store) electrons and holes. A gate electrode, which may be doped (to be conductive) polysilicon, is disposed on the ONO stack, and may be a portion of an elongate wordline extending through the array (or a portion thereof).
An inter-level dielectric (ILD) may be disposed on the substrate to support patterns of metallization for interconnecting cell transistors. A portion of the pattern may comprise metal bitlines (MBLs). Contacts to the buried bitlines may be made by metal-filled plugs extending through the ILD to the buried bitlines, such as at intervals of every 16 cells. (It is generally not necessary to have one bitline contact per cell, and a contact area occupies area which otherwise could be used for cell transistors.)
In some of the memory array illustrations presented herein, the wordlines may extend horizontally through the array (or a portion thereof), and the bitlines may extend vertically through the array (or a portion thereof), intersecting the wordlines at right angles (90 degrees) thereto. Or, in some of the illustrations, the memory array may be rotated so that the wordlines extend vertically and the bitlines extend horizontally.
Generally, the cell transistors described herein may be “dual bit” transistors, such as NROM, having two bit storage (charge-trapping) areas which may be referred to as the “left bit” and the “right bit”.
Drain-Side and Source-Side Sensing
Generally, for an NROM cell having two bit storage areas, one over the drain (D) and another over the source (S), reading the bit over the source (S) may be performed by setting the drain “read” voltage (Vdr) to approximately +2 volts, such as 1.4 volts, and setting the source voltage (Vs) to 0 volts (or ground). For example, with reference to FIG. 3, to read the “right” bit 323, use the left diffusion 314 as drain (D) and the right diffusion 316 as source (S). To read the “left” bit 325, use the right diffusion 316 as drain (D) and the left diffusion 314 as source (S).
With Vdr on the drain (D), the program level (as represented by Vt) stored over the source (S) may be sensed. Generally, to sense the Vt, current is measured, such as the current flowing into the drain (D) or the current coming out of the source (S). Either the drain (D) or the source (S) may be used as the “sensing node”.
Parasitic Capacitances
An issue being addressed by the present disclosure is parasitic capacitance, and the effects thereof.
Generally, in any electronic device, wherever there are two conductors (separated by an insulator), there are capacitances. In some cases, capacitors are advertently constructed, such as in DRAM cells for storing charges, and are considered to be desirable. However, in many cases, the mere presence of conductive lines and elements can introduce “stray”, generally undesirable capacitances, referred to herein as “parasitic capacitances”. A reason that these parasitic capacitances are generally undesirable, in the context of reading memory cells, is that they can “steal” charge, by providing a “leakage” path. So, for example, when trying to read a memory cell programmed to a given voltage, the measured current may appear sufficiently lower to result in a false (erroneous) reading. When current leaks, voltage drops, generally according to the well known Ohm's law where E (voltage)=I (current) times R (resistance). More current leaking means more voltage dropping.
With so many conductive structures crammed together in very small spaces, for example, when operating one metal bitline (MBL) to read the contents of a memory cell, stray capacitance from adjacent MBLs (or LBLs) may cause voltage drops leading to false readings.
This issue is addressed, for example, in US Patent Publication No. 2003/0202411, incorporated by reference in its entirety herein, which discloses a system for control of pre-charge levels in a memory device. As noted therein, some terminals in an array of memory cells may be charged-up to prevent leakage currents which would otherwise adversely influence reading the contents of memory cells.
Pipe Effect Problem Description
In a Virtual Ground Array (VGA), or any other topological architecture where there is an electrical connection between neighboring cells, there is a possibility of current leaking to the neighboring cells, charging the parasitic capacitance associated with these cells (diffusion bit lines—DBLs) and other capacitances which may be connected to these cells.
This parasitic current will affect the sensing current, and thus will create “cross-talk” between cells. (Cross-talk is when the value of one memory cell affects the sensed value of another, typically neighboring, cell. Cross-talk is a different issue than disturb or retention or endurance.)
A “pipe effect” is typically caused due to a difference between the drain/source voltage level of the cell that is being read, to the pipe's, (neighbor cell's) voltage level. The pipe current can either increase or reduce the sensed current, and thus change the apparent logical value of the flash cell. This can be particularly troublesome when reading the contents of multi-level cells. The magnitude of the pipe problem depends on the neighboring flash cell's operating condition (erased or programmed), on the temperature, the word-line level, the parasitic capacitance and more. Thus, it cannot readily be compensated by a simple shift in some parameter or another (such as gate voltage or drain voltage, for example), but should be eliminated as much as possible.
Commonly-owned patents disclose structure and operation of NROM and related ONO memory cells. Some examples may be found in commonly-owned U.S. Pat. Nos. 5,768,192 and 6,011,725, 6,649,972 and 6,552,387.
Commonly-owned patents disclose architectural aspects of an NROM and related ONO array, (some of which have application to other types of NVM array) such as segmentation of the array to handle disruption in its operation, and symmetric architecture and non-symmetric architecture for specific products, as well as the use of NROM and other NVM array(s) related to a virtual ground array. Some examples may be found in commonly-owned U.S. Pat. Nos. 5,963,465, 6,285,574 and 6,633,496.
Commonly-owned patents also disclose additional aspects at the architecture level, including peripheral circuits that may be used to control an NROM array, or the like. Some examples may be found in commonly-owned U.S. Pat. Nos. 6,233,180, and 6,448,750.
Commonly-owned patents also disclose several methods of operation of NROM and similar arrays, such as algorithms related to programming, erasing, and/or reading such arrays. Some examples may be found in commonly-owned U.S. Pat. Nos. 6,215,148, 6,292,394 and 6,477,084.
Commonly-owned patents also disclose manufacturing processes, such as the process of forming a thin nitride layer that traps hot electrons as they are injected into the nitride layer. Some examples may be found in commonly-owned U.S. Pat. Nos. 5,966,603, 6,030,871, 6,133,095 and 6,583,007.
Commonly-owned patents also disclose algorithms and methods of operation for each segment or technological application, such as: fast programming methodologies in all flash memory segments, with particular focus on the data flash segment, smart programming algorithms in the code flash and EEPROM segments, and a single device containing a combination of data flash, code flash and/or EEPROM. Some examples may be found in commonly-owned U.S. Pat. Nos. 6,954,393 and 6,967,896.
Where applicable, descriptions involving NROM are intended specifically to include related oxide-nitride technologies, including SONOS (Silicon-Oxide-Nitride-Oxide-Silicon), MNOS (Metal-Nitride-Oxide-Silicon), MONOS (Metal-Oxide-Nitride-Oxide-Silicon) and the like used for NVM devices. Further description of NVM and related technologies may be found at “Non Volatile Memory Technology”, Vol. 1 & 2 (2005), Vol. 3 (2006) and Vol. 4 (2007), published by Saifun Semiconductor; “Microchip Fabrication”, by Peter Van Zant, 5th Edition 2004; “Application-Specific Integrated Circuits” by Michael John Sebastian Smith, 1997; “Semiconductor and Electronic Devices”, by Adir Bar-Lev, 2nd Edition, 1999; “Digital Integrated Circuits” by Jan M. Rabaey, Anantha Chandrakasan and Borivoje Nikolic, 2nd Edition, 2002 and materials presented at and through http://siliconnexus.com, “Design Considerations in Scaled SONOS Nonvolatile Memory Devices” found at: http://klabs.org/richcontent/MemoryContent/nvmtsymp/nvmts—2000/presentations/buwhites onos_lehigh_univ.pdf, “SONOS Nonvolatile Semiconductor Memories for Space and Military Applications” found at: http://klabs.org/richcontent/MemoryContent/nvmtsymp/nvmts—2000/papers/adams_d.pdf, “Philips Research-Technologies-Embedded Nonvolatile Memories” found at: http://www.research.philips.com/technologies/ics/nvmemoriesindex.html, and “Semiconductor Memory: Non-Volatile Memory (NVM)” found at: http://www.ece.nus.edu.sg/stfpage/elezhucx/myweb/NVM.pdf,
all of which are incorporated by reference herein in their entirety.